Semiconductor manufacturing apparatus

ABSTRACT

A manufacturing apparatus for semiconductor devices comprises as a halogen scavenger a silicon ring ( 12 ) having an average surface roughness of 1-1000 μm, arranged around a silicon substrate ( 6 ) on a lower electrode ( 3 ) in a reaction chamber ( 7 ); and an upper silicon element ( 5 ) as another halogen scavenger, having an average surface roughness of 1-1000 μm, arranged above the silicon substrate ( 6 ). In this apparatus, C 2 F 6  is used as a gas to be introduced into the chamber ( 7 ) and fluorine can be effectively scavenged in the initial phase of operation, so that semiconductor devices can be aged faster than in conventional apparatus.

FIELD OF THE INVENTION

The present invention relates to a dry-etching apparatus forsemiconductor devices.

BACKGROUND OF THE INVENTION

In recent years, the integration degree of semiconductor devices hasrisen remarkably. The increase of the integration degree is sustained byadvances in process techniques. Especially, advances in photolithographytechniques and dry etching techniques play a great role for the rise ofthe integration degree. In recent dry-etching techniques, a tendency canbe observed toward the active use, from the view point ofminiaturization, of a low gas pressure, high density plasma. Consideringsuch a background, dry-etching apparatus using an electron cyclotronresonance plasma, an inductive coupling type plasma or a helicon waveexcitation plasma have been developed and sold (see for example:“Semiconductor World” Oct. issue 1993, pp. 68-75).

Below, an example for a conventional oxide film etching apparatus isexplained with reference to FIG. 1, which shows an apparatus using aninductive coupling type plasma.

In FIG. 1, numeral 1 is an induction coil and numeral 2 is a highfrequency power source, which supplies the induction coil 1 with highfrequency electricity. Numeral 3 is a lower electrode and numeral 4 is ahigh frequency power source, which supplies the lower electrode 3 withhigh frequency voltage. Numeral 5 is an upper silicon electrode andnumeral 6 is a silicon substrate placed on the lower electrode 3 andarranged in parallel to the upper silicon electrode 5 within at reactionchamber 7. Numeral 8 is a pressure control valve and numeral 9 is anexhaust pump, by which a predetermined pressure is maintained in thereaction chamber 7. Numeral 10 is a gas bottle, supplying C₂F₆ to thereaction chamber 7 through a mass flow 13. Numeral 11 is a heater, whichmaintains the upper silicon electrode 5 at a constant temperature.Numeral 12 is a silicon ring, which is arranged to enclose the siliconsubstrate 6 on the lower electrode 3. Numeral 13 is a mass flow andnumeral 14 is a matcher to attain impedance matching between the highfrequency power source 4 and the lower electrode 3.

C₂F₆ is introduced into the reaction chamber 7 from the gas bottle 10and maintained at a predetermined pressure. A plasma is generated in thereaction chamber 7 by supplying the induction coil 1 with high frequencyelectric power from the high frequency power source 2. Ions from theplasma are attracted by impressing a bias voltage onto the lowerelectrode 3 with the high frequency power source 4, so that the siliconsubstrate 6 is etched.

The silicon ring 12 and the upper silicon electrode 5 (which arereferred to as silicon members below) realize a high etching speed ratioof the oxide film against the silicon substrate 6 by decreasing thefluorine in the plasma due to a reaction with silicon (see FIG. 2 B).This silicon member has a smooth surface, and as is shown in FIG. 3B,the average roughness of the irregularities H of the surface is about0.1 μm.

Numeral 15 of FIG. 4 is an example for the relationship betweenoperating time T and selectivity ratio R for the etch rate of the oxidefilm of the silicon substrate with respect to the resist, whenconventional silicon members with a smooth surface are used.

A constant time period is necessary so that the silicon members canscavenge halogen elements. After such aging is finished, a stable etchrate is attained.

However, as can be gathered from numeral 15 of FIG. 4, in a conventionalmanufacturing apparatus using silicon members with a smooth surface, along period of time is necessary to stabilize the selectivity ratio Rfor the etch rate of the oxide film with respect to the resist. Thatmeans, there was the problem that a long aging time is necessary to putthe silicon members into a condition where they can scavenge halogenelements.

SUMMARY OF THE INVENTION

In order to solve the problems of the prior art, it is a purpose of thepresent invention to provide a manufacturing apparatus for semiconductordevices, which can abbreviate the aging time by having a halogenscavenger with irregularities on its surface.

In order to attain this purpose, a manufacturing apparatus forsemiconductor devices according to the present invention comprises ahalogen scavenger having tiny irregularities on its surface in areaction chamber of a dry-etching apparatus and the average roughness ofthose tiny irregularities is 1-1000 μm.

Because such a manufacturing apparatus for semiconductor devicescomprises a halogen scavenger having irregularities on its surface, theeffective surface area for halogen elements is maintained from aninitial condition, so that the aging time is abbreviated.

When the average roughness of those tiny irregularities in themanufacturing apparatus for semiconductor devices is 1-1000 μm, theaging time can be abbreviated and an unfavorable influence such as anetching stop can be prevented.

It is preferable that the average roughness of the tiny irregularitiesin the manufacturing apparatus for semiconductor devices is 1-10 μm.

It is preferable that the halogen scavenger in the manufacturingapparatus for semiconductor devices comprises at least one materialselected from the group consisting of silicon and carbon.

It is preferable that the halogen scavenger in the manufacturingapparatus for semiconductor devices is a silicon ring arranged aroundthe silicon substrate to be etched.

It is preferable that the halogen scavenger in the manufacturingapparatus for semiconductor devices is an upper silicon electrodearranged above the silicon substrate to be etched.

It is preferable that the irregularities in the manufacturing apparatusfor semiconductor devices are produced by wet-etching.

It is preferable that a gas used for dry-etching in the manufacturingapparatus for semiconductor devices is C₂F₆.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an etching apparatus for semiconductor devicesaccording to an example of the present invention.

FIG. 2A is a model diagram showing the principle underlying an apparatusaccording to the present invention.

FIG. 2B is a model diagram showing the principle underlying aconventional apparatus.

FIG. 3A is an enlarged view of the surface of a halogen scavenger in anexample of an apparatus according to the present invention.

FIG. 3B is an enlarged view of the surface of a halogen scavenger in anexample of a conventional apparatus.

FIG. 4 shows the relationship between operating time T of an apparatusaccording to the present invention and selectivity ratio R of the oxidefilm etch rate of the silicon substrate against the resist, compared tothe situation in a conventional apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The aspect in which the manufacturing apparatus for semiconductordevices differs the most from said conventional apparatus is that ashalogen scavengers, that means the silicon ring 12 and the upper siliconelectrode 5, members with a rough surface having irregularities areused.

An example of the present invention is explained below with reference tothe drawings. The basic structure of this example of an apparatus isshown in FIG. 1. Because the structure is similar to conventionalexamples, a detailed explanation has been omitted. C₂F₆ was used as agas to be introduced into reaction chamber 7. The pressure of the gaswas set to 5×10³ Torr. The average roughness of the surfaceirregularities H of the silicon ring 12 and the upper silicon electrode5 was made to be at least 1 μm and at least 10 times the surfaceroughness of conventional halogen scavengers, as can be seen in FIG. 3A.Under the surface condition (surface morphology) in FIG. 3A, the crystalgrain boundaries emerge, an aspect that is different from the surfacecondition in FIG. 3B.

By making the surface of the halogen scavengers, namely the silicon ring12 and the upper silicon electrode 5, a rough surface, fluorine can bescavenged from the initial operating condition of the manufacturingapparatus. This mechanism is schematically shown in FIG. 2A. FIG. 2Bshows the scavenging mechanism for a conventional member.

As becomes clear from the models shown in FIGS. 2A and 2B, when thehalogen scavenger has a big effective surface area, more fluorine can bescavenged. However, an effective surface area that is too big has anunfavorable influence on performance characteristics and may cause theetching to stop because too much fluorine is scavenged, so it ispreferable that the surface roughness is not more than 1000 μm.

Consequently, the average roughness of the irregularities of the halogenscavengers is preferably in a range of 1-1000 μm, more preferable is arange of 1-10 μm.

The rough surface of such a halogen scavenger can be produced bywet-etching. In this example, a solvent of hydrogen fluoride (HF) andnitric acid (HNO₃) mixed in a ratio of 1:10 was used to performwet-etching at 25° C. fluid temperature for 30 min.

FIG. 4 shows the relationship between the operating time T of anapparatus according to the present invention, which uses a halogenscavenger with large surface roughness and the selectivity ratio R ofthe oxide film etch rate of the silicon substrate against the resist,compared to the situation in a conventional apparatus. Numeral 15indicates the measured results for a conventional example and numeral 16the results for an example according to the present invention.

In the example of the present invention, a halogen scavenger with 3 μmaverage roughness of the irregularities was used. In the example of aconventional apparatus, a halogen scavenger with 0.2 μm averageroughness of the irregularities was used. In both the example of thepresent invention and the conventional apparatus, a silicon ring with210.4 mm internal diameter, 272.9 mm external diameter and 12.9 mmthickness was used.

As becomes clear from FIG.4, in the example of the present invention asindicated by numeral 16, the time to reach a stable selectivity ratio Rof the oxide film etch rate of the silicon substrate against the resistis shorter than in a conventional apparatus as indicated by numeral 15.For example, if a standard value for the selectivity ratio R of theoxide film etch rate against the resist is assumed to be 7.5, theconventional example as indicated by numeral 15 needs 32.5 hours agingtime to reach the standard value 7.5, whereas the present example asindicated by numeral 16 needs no aging time at all.

Silicon was used for the halogen scavenger in the present example, butof course the same effect can also be attained by using carbon instead.

As has been explained above, the aging time can be abbreviated by usinga manufacturing apparatus for semiconductor devices according to thepresent invention, which comprises a halogen scavenger withirregularities on its surface.

INDUSTRIAL APPLICABILITY

The manufacturing apparatus for semiconductor devices according to thepresent invention can be used as a dry-etching apparatus of siliconsubstrates for semiconductor devices, because the aging time fordry-etching can be abbreviated.

What is claimed is:
 1. A dry-etching method, comprising: placing ahalogen scavenger in a reaction chamber of a dry-etching apparatus usinga plasma, the halogen scavenger having a surface on which tinyirregularities with an average roughness in a range between 1-1000 μmare formed and being able to scavenge fluorine contained in the plasma;placing a substrate in the reaction chamber, the substrate having anoxide film and a resist film formed thereon; and carrying outdry-etching of the oxide film formed on the substrate using a gascontaining C and F, wherein the dry-etching is started directly afterinitial placement of the substrate in the reaction chamber after placingthe halogen scavenger in the reaction chamber and is carried out under acondition in which a selectivity ratio of the oxide film etch rateagainst the resist film is below a standard value for carrying out thedry-etching stably.
 2. The dry-etching method according to claim 1,wherein the average roughness of the tiny irregularities is 1-10 μm. 3.The dry-etching method according to claim 1, wherein the tinyirregularities are produced by wet-etching.
 4. The dry-etching methodaccording to claim 1, wherein the halogen scavenger comprises at leastone material selected from the group consisting of silicon and carbon.5. The dry-etching method according to claim 1, wherein the halogenscavenger is a silicon ring arranged around a silicon substrate to beetched.
 6. The dry-etching method according to claim 1, wherein thehalogen scavenger is an upper silicon electrode arranged above a siliconsubstrate to be etched.
 7. The dry-etching method according to claim 1,wherein a gas used for the dry-etching is C₂F₆.